1. Field of the Invention
The present invention relates to a peripheral circuit that operates in accordance with instructions from a CPU. More particularly, the present invention relates to the implementation of a register for writing commands inside an apparatus for performing a desired operation by receiving an instruction from a CPU.
2. Description of the Related Art
In electronic systems such as digital cameras, there have been increasing demands for more complex processing. When such complex processing is to be performed by a single CPU, the load on the CPU increases, and the performance of the entire system thus decreases. However, if a large number of CPUs are installed to distribute the processing, the cost increases. For this reason, it is common practice that the electronic system is formed of a CPU and peripheral devices that perform complex operations in accordance with simple commands from the CPU. In such an electronic system, the CPU gives instructions to peripheral devices, etc., so that a series of sequences is performed.
For example, in the driving of an optical sensor of a digital camera, the CPU detects that the release button of the camera main unit is half pressed, instructs the shape of a driving waveform to a timing pulse generation device for generating a driving pulse of the optical sensor, instructs a read-out area to the optical sensor, instructs the specification of an amplification ratio and the calibration operation of an offset level to an A/D converter for converting an optical sensor output to digital values, and instructs a reference voltage to a D/A converter for generating a reference voltage. Thereafter, it is necessary to detect that the release button is fully pressed and to notify many commands, such as instructions for starting the operation of the optical sensor and the A/D converter, to the peripheral device and the sensor.
In the electronic system requiring real-time processing, such as a digital camera, the CPU needs to perform these communications at an appropriate timing, and there are many cases in which the communication speed of the peripheral device is not so high. For this reason, when an operation is performed with a communication rate matching a peripheral device, communication from the CPU to the peripheral device becomes an overhead of the system, and a side effect, such as a time lag in the shutter operation, appears. In order to deal with such a side effect, many electronic systems adopt a configuration in which the CPU performs communication only with a specific peripheral device having a high communication speed and this peripheral device performs communication with the other peripheral device having a low communication speed in place of the CPU, so that the overhead of the CPU, which is involved with communication, is reduced. For communication between the CPU and the specific peripheral device having a high communication speed, it is common practice that, for example, a burst mode is used in which, for first data, the corresponding address is transmitted, and thereafter, only the data is transmitted by assuming that the address is automatically incremented for each piece of data, so that speed increases.
FIG. 5 shows a specific example of the configuration of an imaging section of a digital camera. A CPU 501 controls an image capturing sequence. A peripheral device 502 takes over the communication of the CPU 501. A timing pulse generation device 503 controls the operation timing of the optical sensor and an A/D (analog-to-digital) converter 506. A D/A (digital-to-analog) converter 504 provides a reference voltage to an optical sensor 505. The CPU 501 and the peripheral device 502 communicate via a high-speed communication line 507 connected therebetween. A comparatively low-speed communication line 508 is used for communication among the peripheral device 502, the timing pulse generation device 503, the D/A converter 504, the optical sensor 505, and the A/D converter 506. Output from the optical sensor is transmitted to the A/D converter 506 via an optical-response analog output line 509. An optical output from the A/D converter is digitized via an output line 510. The reference voltage of the D/A converter 504 is output via an output line 511. Timing pulse output lines 512 and 513 are provided from the timing pulse generation device to the optical sensor 505 and the A/D converter 506, respectively.
The CPU 501, through the comparatively high-speed communication line 507, writes a desired value in a plurality of registers for storing parameters for controlling the operation of the timing pulse generation device 503 incorporated in the peripheral device 502, and writes a command for communicating the values stored in the plurality of registers to the timing pulse generation device 503 into the command register of the peripheral device 502. As a result, in place of the CPU 501, the peripheral device 502 performs the setting of necessary parameters in the timing pulse generation device 503 through the comparatively low-speed communication line 508.
Similarly, by also writing into the internal register of the peripheral device 502 for the purpose of setting the D/A converter 504, the optical sensor 505, and the A/D converter 506, the peripheral device 502, in place of the CPU, performs communication with the D/A converter 504, the optical sensor 505, and the A/D converter 506 through the comparatively low-speed communication line 508.
FIG. 7 shows the configuration of a register incorporated in the peripheral device 502 for performing communication in place of the CPU in a conventional electronic system. Each rectangle indicates a one-word register. Register groups 702, 703, and 704 shown in FIG. 7 are used for holding parameters to be written into the timing pulse generation device 503, the D/A converter 504, and the optical sensor 505 of FIG. 5. For the sake of simplicity in the figures, here, the register group for holding parameters to be written into the A/D converter 506 is not shown. A command register 701 is used for writing commands. As described above, in order to perform communication with the timing pulse generation device 503, the CPU 501 sets parameters in the register group indicated by 702, and then writes a command for performing communication with the timing pulse generation device 503 in the command register indicated by 701.
FIG. 6 shows a conventional example of a waveform when this communication is performed by serial communication in the burst mode. CS denotes a chip select signal in serial communication. SCLK denotes a communication clock in serial communication. SD denotes data in serial communication.
The low state of the chip select signal CS indicates the effective period of the communication data. An operation of writing data SD into the register of FIG. 7 is performed in synchronization with the rise of the communication clock SCLK of the low period. The period indicated by 601 in FIG. 6 is a flag indicating the read and write direction of the serial communication. The period indicated by 602 is an address at which data is to be written. The period indicated by 603 is data to be written at the address 602. Since this communication is burst-mode communication, reference numeral 604 denotes data to be written at the next address. Reference numeral 605 denotes the last written data of burst-mode communication. A flag indicating the read and write direction of a second serial communication is indicated by 607. A command to be written into the command register is indicated by 606.
In the manner described above, as a result of writing parameters in the burst-mode serial communication and writing commands in the normal-mode serial communication thereafter, it becomes possible for the peripheral device 502 of FIG. 5 to communicate with the timing pulse generation device 503, the D/A conversion device 504, the optical sensor 505, and the A/D converter 506, which are the other peripheral devices.
As another related technology, Japanese Patent Laid-Open No. 9-261278 is also known.
However, in the conventional method, it is necessary to separately perform serial communication in the burst mode for setting parameters and serial communication for writing commands. For this reason, firmware for performing serial communication with the peripheral device 502 becomes complex in the CPU, and also, the communication takes time, and an overhead occurs.